1. Field of the Invention
The present invention relates to a method of trimming a reference cell in a semiconductor memory device, a semiconductor memory device, and a parallel trimming apparatus.
2. Description of the Related Art
Semiconductor memory devices are devices in which data can be stored and from which stored data can be retrieved. Semiconductor memory devices can be classified into volatile memory and nonvolatile memory. The nonvolatile memory devices comprise electrically erasable and programmable ROM cells, known as flash EEPROM cells. FIG. 1 shows a vertical cross-section of a flash EEPROM cell 10. Referring to FIG. 1, an N-type source region 13 and an N-type drain region 14 are formed on a P-type substrate or a bulk region 12. A p-type channel region is formed between the source region 13 and the drain region 14. A floating gate 16, which is insulated by an insulating layer 15, is formed on the P-type channel region. A control gate 18, which is insulated by another insulating layer 17, is formed on the floating gate 16.
FIG. 2 shows threshold voltages of the flash EEPROM cell 10 during program and erase operations. Referring to FIG. 2, the flash EEPROM cell 10 has a higher threshold voltage range (about 6 to 7V) during the program operation, and has a lower threshold voltage range (about 1 to 3V) during the erase operation.
Referring to FIG. 1, in order to program the EEPROM cell 10, a high positive voltage (e.g. 10V) is applied to the control gate 18 of the cell 10. In addition, a moderate positive voltage (e.g. 4.5V) is applied to the drain region 14, and the source voltage and the substrate voltage are at ground level. During the program operation, hot electrons need to be injected from the channel region adjacent to the drain region 14 to the floating gate electrode, so that the threshold voltage of the EEPROM cell increases.
In order to erase the EEPROM cell 10, a negative voltage (e.g. −10V) is applied to the control gate 18 of the cell 10. In addition, the source region 13 of the cell 10 is set to 5.5 V and the drain region 14 of the cell 10 is allowed to float. During the erase operation, the hot electrons injected into the floating gate 16 during the program operation need to be removed, so that the threshold voltage of the EEPROM cell decreases.
To verify whether an EEPROM cell has been erased or programmed, a reference cell is used to verify the state of the EEPROM cell. For example, a current of the EEPROM cell is compared to a current of the reference cell, and the result of the comparison is used to identify whether the memory cell is a program cell or an erase cell. Thus, generating an accurate current of the reference cell is important in determining the state of the EEPROM cell.
The reference cells are pre-programmed or trimmed by the manufacture of the memory to produce a specific reference current in response to a known gate voltage. FIG. 3 is a block diagram of a conventional semiconductor memory device 30 for performing the reference cell trimming. Referring to FIG. 3, the semiconductor memory device 30 comprises a reference cell 302, an I/O pad 304, a comparator 306 and a voltage supply controller 308. During the trimming process of the reference cell 302, the reference cell 302 is programmed in response to a bias voltage VB supplied by the voltage supply controller 308.
A reference cell current Iref flows between a drain region and a source region of the reference cell 302 in response to the bias voltage VB. The comparator 306 compares an external bias current Ix input from a tester (not shown) via the I/O pad 304 with the reference cell current Iref and outputs a comparison signal CS. The voltage supply controller 308 receives the comparison signal CS and supplies the bias voltage VB to the reference cell 302 based on the comparison signal CS. When the reference cell current Iref is within the given error range of the external bias current Ix, the reference cell trimming terminates.
In the conventional reference trimming in a semiconductor memory device, a tester must provide a constant current via the I/O pad. If there are eight reference cells to be trimmed, eight separate constant currents require to be supported to the eight semiconductor memory device on a test board. Such trimming apparatus requires complex hardware and software to use. Moreover, it is difficult to precisely measure the current to be with the desired range during the production process, and thus it requires a large amount of trimming test time for the reference cells in the semiconductor memory devices and increases labor costs. In order to solve the foregoing problems, there is a need to provide an improved trimming method and trimming apparatus.